Atmel AVR Microcontrollers

The AVR microcontroller architecture designed by Atmel is based on an 8-bit RISC CPU core. AVR devices contain a CPU, flash program memory, SRAM and EEPROM for storing program data, and I/O peripherals, including digital GPIO pins, serial communication interfaces compatible with the I²C and SPI buses, programmable timers and PWM outputs, and analog-to-digital converters.


Several families of AVR devices are made for different applications. The common general-purpose families include the tinyAVR (ATtiny* parts) and more powerful megaAVR (ATmega* parts). Special-purpose devices are also made for automotive applications, USB peripherals, and lighting control.

All AVR parts use the same CPU and memory architecture, with variations on the instructions and types and sizes of memory available. Various peripherals are included in different models such as timers, analog-to-digital converters, and serial communications hardware.

CPU Core

The AVR CPU uses a RISC design and is implemented with a 2-stage pipeline. Most simple ALU instructions execute in 1 clock cycle, allowing "throughput approaching 1 MIPS per MHz" according to Atmel, with other instructions such as memory access requiring 2 clock cycles. Instructions available vary across different models, with features such as hardware multiplier only available on the megaAVR family.

The CPU can be driven by a clock running at up to 10 or 20 MHz on most devices. This can be provided either by an external crystal oscillator for high accuracy, or an internal RC oscillator can be used to reduce the circuit complexity.


Up to four types of memory are available on most AVR devices. All models include a set of 32 8-bit general purpose registers and some amount of flash memory for storing program code. Most larger devices also include a small amount of SRAM data memory and non-volatile EEPROM.

Unlike most general-purpose microprocessors, but like many microcontroller designs, the AVR CPU uses the Harvard architecture, meaning that program instructions and data are stored in different sections of memory.


The basic IO peripherals are digital GPIO pins that can be used for reading and writing digital signals. These are arranged into ports of up to 8 bits. Each port has two IO registers associated with it: a data direction register that configures individual pins for input or output mode, and a data register to read or write the value of each pin.

More specialized peripherals are also included on most devices.


AVR timer/counters consist of a bi-directional binary counter, usually 8 or 16 bits and logic to advance the counter from an internal or external clock source and trigger interrupts or change timer behavior when the counter reaches certain values. The different timer modes can be used for timing program code to be run at specific intervals, timing external pin-change events, or generating PWM waveforms. Most parts have 1, 2, or 3 independent timers supporting some or all of these extended features.

The CPU clock is connected to each timer through a prescaler that can advance the counter at the same or a fraction of the main frequency.

In normal mode, the timer starts counting up at 0 until it reaches its maximum value and then resets, optionally triggering a timer overflow interrupt.

Timers also include 2 output compare registers that are used in the other modes. In clear timer on compare match mode (CTC), the counter resets when it reaches the output compare value instead of continuing all the way to its maximum value. This allows the timer duration to be changed with more precision than just the prescaler.

Two PWM modes are also implemented: fast PWM and phase-compare PWM. Both of these modes will automatically change the state of an output pin when the counter reaches the value in one of the output compare registers. In fast PWM mode, the timer counts upward from 0, generating a sawtooth wave. The output pulse is created by toggling the pin state once at the beginning of the cycle and again when it reaches the compare value. In phase-correct PWM mode, a symmetric triangle wave is created up and then down. The output pin is toggled once on the increasing slope and once on the decreasing slope, so that pulses of varying length will still be centered at regular intervals.

Analog Input

Serial Communications

Other Components


Languages and Compilers

Hardware Interfaces

-- StephenCavilia - 2009-11-02
Topic revision: r4 - 07 Dec 2009, StephenCavilia
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding CodenamePending? Send feedback